A. Field of the Invention
The present invention relates generally to computer architecture design, and more particularly to a personal computer architecture design that improves system performance including video display performance by positioning a video control circuit in a direct path with a processing unit.
B. Description of the Related Art
Since the introduction of the IBM Personal Computer (PC will be used herein to refer not only to the IBM Personal Computer but also later-developed IBM PC clones or compatible machines) in the early 1980's to the present day, there has developed a de facto industry standard for at least a core portion of the PC's system architecture. This core portion, shown in an oversimplified manner in FIG. 1, is followed by all PC designers to maintain compatibility among different generations of PCs for the numerous application software programs that have been developed.
With further reference to FIG. 1, a typical PC system architecture includes a processing unit consisting of a microprocessor and possibly a cache controller and co-processor, a memory unit, and an input/output (I/O) unit including a peripheral bus (referred to herein also as the Industry Standard bus or simply ISA bus) for connecting to expansion slots where optional peripheral devices may be inserted.
The ISA bus, which has been a part of the core design from the inception of the PC, is used to connect a variety of option boards or peripheral devices to the system or "mother board." This arrangement has provided great flexibility in configuring a PC to suit the needs of each user. The increased flexibility, however, has been at the expense of the PC's overall performance. That is, the greater flexibility usually results in slower system performance. As a result, many designers have elected to parse functions off the ISA bus. For example, many companies now provide dedicated interfaces from the microprocessor to the extended and expanded memories or hard disks.
The inventors have identified the transfer of video signals to the video controller as another one of these "bottlenecks" of the PC. Today, in accordance with the de facto standard, in order to display an image, data travels from the processor to the I/O block to the video circuit via the ISA bus, where finally the data is converted to video signals and sent to a display unit. This architecture has, at least with respect to the display of video signals, the following disadvantages. First, while the processor operates typically in the range of 16 to 33 MHz, the ISA bus transfers data only at 8 MHz. Thus, data is transferred across the ISA bus at a much slower rate. Moreover, the ISA bus operates asynchronous to the processor, and therefore the data must be resynchronized to the rate of the ISA bus prior to being transferred. Second, it is possible that the peripheral device is not the only agent trying to gain access to a processor via the ISA bus. Hence, the peripheral device must "wait its turn" prior to completing the instruction and transfer, as well as the processor must wait until an acknowledgment is received from the peripheral device that it has completed its instruction and transfer. Thus, by transferring data from the processor to the video circuit over the local bus, the performance of both the processor and peripheral device is accelerated, consequently improving overall system performance Third, the constant updating of the video display requires numerous accesses to the video circuit which means that the processor does not make infrequent trips to the video circuit, but rather spends an enormous amount of time sending and retrieving data from the video circuit. Moreover, as the more sophisticated software application programs become more and more display intensive, this constant updating only increases, resulting in very frequent trips to and from the video circuitry.
The inventors are aware of one proprietary system architecture that attempts to overcome the above problems. Generally, the proprietary method features a video circuit "straddling" a 82396SX (type designation of Intel Corp.) cache controller, such that the video circuit interfaces with address signals outputted by a 80386SX (type designation of Intel Corp.) microprocessor and with data signals outputted by the 82396SX cache controller. This design, however, is disadvantageous for the following reasons. First, it is designed specifically for a 80386SX microprocessor and 80396SX cache controller. Thus, this design is rendered useless with the newly introduced 80486 (type designation of Intel Corp.) microprocessor which incorporates a cache controller therein, or any of the next generation microprocessors. Second, the proprietary design cannot take advantage of the write post FIFO of the 82396SX cache controller, which is an important feature thereof, and therefore suffers severe performance penalties. Further, because of the peculiar nature of the design (i.e., because it straddles the cache controller) this design has very tight timing tolerances requiring fast and expensive components, which results in higher manufacturing cost.